Title
An energy efficient multi-target binary translator for instruction and data level parallelism exploitation
Abstract
Embedded devices are omnipresent in our daily routine, from smartphones to home appliances, that run data and control-oriented applications. To maximize the energy-performance tradeoff, data and instruction-level parallelism are exploited by using superscalar and specific accelerators. However, as such devices have severe time-to-market, binary compatibility should be maintained to avoid recurrent engineering, which is not considered in current embedded processors. This work visited a set of embedded applications showing the need for concurrent ILP and DLP exploitation. For that, we propose a Hybrid Multi-Target Binary Translator (HMTBT) to transparently exploit ILP and DLP by using a CGRA and ARM NEON engine as targeted accelerators. Results show that HMTBT transparently achieves 24% performance improvements and 54% energy savings over an OoO superscalar processor coupled to an ARM NEON engine. The proposed approach improves performance and energy in 10%, 24% over decoupled binary translators using the same accelerator with the same ILP and DLP capabilities.
Year
DOI
Venue
2022
10.1007/s10617-021-09258-6
Design Automation for Embedded Systems
Keywords
DocType
Volume
CGRA, ARM NEON, ILP, DLP, Binary Translator
Journal
26
Issue
ISSN
Citations 
1
0929-5585
0
PageRank 
References 
Authors
0.34
3
7