Paper Info
Title
An Accurate Estimation Algorithm for Failure Probability of Logic Circuits Using Correlation Separation
Abstract
As the feature size of integrated circuits decreases to the nanometer scale, process fluctuations, aging effects, and particle radiation have an increasing influence on the Failure Probability of Circuits (FPC), which brings severe challenges to chip reliability. The accurate and efficient estimation of logic circuit failure probability is a prerequisite for high-reliability design. It is difficult to calculate FPC due to a large number of reconvergent fanout structures and the resulting signal correlation, particularly for Very Large-Scale Integrated (VLSI) circuits. Accordingly, this paper presents a Correlation Separation Approach (COSEA) that aims to efficiently and accurately estimate the FPC. The proposed COSEA divides the circuit into several different fanout-relevant and fanout-irrelevant circuits. Moreover, the error probability of the nodes is expressed as the result of interactions between different structures. As a result, the problem of signal correlation can be efficiently solved. Because the computational complexity of COSEA is linearly related to the scale of the circuit, it has good scalability. Compared with the Probabilistic Transfer Matrices (PTM) method, Monte Carlo simulation (MC), and other failure probability calculation methods in the literatures, the experimental results show that our approach not only achieves fast speed and good scalability, but also maintains high accuracy.
Year
DOI
Venue
2022
10.1007/s10836-022-05996-y
Journal of Electronic Testing
Keywords
DocType
Volume
Logic circuit, Failure probability, Correlation separation, Reliability design
Journal
38
Issue
ISSN
Citations 
2
0923-8174
0
PageRank 
References 
Authors
0.34
25
6
Name
Order
Citations
PageRank
Shuo Cai100.34
Binyong He200.34
Sicheng Wu300.34
jin wang424336.79
Weizheng Wang5268.16
Fei Yu600.34