Name
Title | ||
|---|---|---|
A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS |
Abstract | ||
|---|---|---|
This article presents a delta sigma modulator (DSM) analog to digital (ADC) that uses ring amplifiers as integrators to relax speed and efficiency bottlenecks in discrete-time (DT) oversampled ADCs. Its multi-bit quantizer is based on split source (SS) comparators, adding flexibility and power efficiency. The complete oversampling ADC is designed as a 3rd-order cascade of integrator with feed forward (CIFF) with a 4-bit quantizer, and it achieves a peak signal-to-noise and distortion ratio (SNDR) of 67 dB and DR of 70.0 dB with 47.5-MHz bandwidth when clocked at 950 MHz. This is the highest bandwidth reported to date among single-channel DT DSM ADCs and demonstrates a viable alternative to continuous-time (CT) DSM ADCs for wideband oversampling applications. With a power consumption of 4.7 mW from a 1-V supply, figure of merit (FoM) Schreier and Walden are 167.0 dB and 27.0 fJ/c.s, respectively, demonstrating efficient DT delta-sigma conversion with high bandwidth. |
Year | DOI | Venue |
|---|---|---|
2022 | 10.1109/JSSC.2022.3163819 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
Cascade of integrators with feed forward (CIFFs),delta-sigma modulation,discrete-time (DT) analog to digital (ADC),oversampling ADC,ring amplification | Journal | 57 |
Issue | ISSN | Citations |
7 | 0018-9200 | 0 |
PageRank | References | Authors |
0.34 | 3 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Lucas Moura Santana | 1 | 0 | 0.68 |
| Ewout Martens | 2 | 1 | 1.03 |
| Jorge Lagos | 3 | 18 | 5.57 |
| Benjamin P. Hershberg | 4 | 180 | 23.21 |
| Piet Wambacq | 5 | 56 | 10.11 |
| Jan Craninckx | 6 | 756 | 181.43 |