Name
Abstract | ||
|---|---|---|
The look-up-table (LUT) is widely used in the field of the field programmable gate arrays (FPGA), in which the high efficiencies of energy consumption, area, and speed are primarily concerned. In this paper, a new interconnected LUT structure constructed by the core element of the magnetoelectric spin–orbit logic (MESO) device is proposed. A SPICE model of a MESO-LUT circuit to achieve a two-input logic function is established by which the writing, reading and standby power consumptions are investigated. Comparing with the state-of-art LUT designs based on spin–orbit torque device, resistive switching memory and clockless spin-based LUT, the number of the auxiliary transistors of the proposed 6-input MESO-LUT respectively decreased ∼ 13% , ∼41% and ∼ 81%,due to the property of representing the information by current direction which is promising in the future low power application scenario. |
Year | DOI | Venue |
|---|---|---|
2022 | 10.1016/j.mejo.2022.105493 | Microelectronics Journal |
Keywords | DocType | Volume |
Reconfigurable logic,Look up table (LUT),Spin-based Memory Cell,Magnetoelectric (ME),Spin–orbit (SO) | Journal | 126 |
ISSN | Citations | PageRank |
0026-2692 | 0 | 0.34 |
References | Authors | |
0 | 8 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Junwei Zeng | 1 | 0 | 0.34 |
| Nuo Xu | 2 | 0 | 0.34 |
| Cheng Li | 3 | 279 | 39.13 |
| Desheng Ma | 4 | 0 | 0.34 |
| Chenglong Huang | 5 | 0 | 0.34 |
| Wenqing Wang | 6 | 0 | 0.34 |
| Yihong Hu | 7 | 0 | 0.34 |
| Liang Fang | 8 | 6 | 3.79 |