Name
Abstract | ||
|---|---|---|
Emerging persistent memory (PM) with fast persistence and byte-addressability physically shares the memory channel with DRAM-based main memory. We experimentally uncover that the throughput of application accessing DRAM collapses when multiple threads access PM due to head-of-line blockage in the memory controller within CPU. To address this problem, we design a PM-Accessing Thread Scheduling (PATS) mechanism that is guided by a contention model, to adaptively tune the maximum number of contention-free concurrent PM-threads. Experimental results show that even with 14 concurrent threads accessing PM, PATS is able to allow only up to 8% decrease in the DRAM-throughput of the front-end applications (e.g., Memcached), gaining 1.5x PM-throughput speedup over the default configuration. |
Year | DOI | Venue |
|---|---|---|
2022 | 10.23919/DATE54114.2022.9774762 | PROCEEDINGS OF THE 2022 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2022) |
Keywords | DocType | ISSN |
Persistent Memory, Memory Contention, Thread Scheduling | Conference | 1530-1591 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shucheng Wang | 1 | 1 | 2.05 |
| Qiang Cao | 2 | 593 | 57.50 |
| Ziyi Lu | 3 | 1 | 2.05 |
| Hong Jiang | 4 | 2137 | 157.96 |
| Yuanyuan Dong | 5 | 0 | 0.68 |