Paper Info
Title
Self-Terminating Write of Multi-Level Cell ReRAM for Efficient Neuromorphic Computing
Abstract
The Resistive Random-Access-Memory (ReRAM) in crossbar structure has shown great potential in accelerating the vector-matrix multiplication, owing to the fascinating computing complexity reduction (from O(n(2)) to O(1)). Nevertheless, the ReRAM cells still encounter device programming variation and resistance drifting during computation (known as read disturbance), which significantly hamper its analog computing precision. Inspired by prior precise memory programming works, we propose a Self-Terminating Write (STW) circuit for Multi-Level Cell (MLC) ReRAM. In order to minimize the area overhead, the design heavily reuses inherent computing peripherals (e.g., Analog-to-Digital Converter and Trans-Impedance Amplifier) in conventional dot-product engine. Thanks to the fast and precise programming capability of our design, the ReRAM cell can possess 4 linear distributed conductance levels, with minimum latency used for intermediate resistance refreshing. Our comprehensive cross-layer (device/circuit/architecture) simulation indicates that the proposed MLC STW scheme can effectively obtain 2-bit precision via a single programming pulse. Besides, our design outperforms the prior write&verify schemes by 4.7x and 2x in programming latency and energy, respectively.
Year
DOI
Venue
2022
10.23919/DATE54114.2022.9774550
PROCEEDINGS OF THE 2022 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2022)
Keywords
DocType
ISSN
ReRAM, Programming, Multi-Level Cell, Read Disturbance
Conference
1530-1591
Citations 
PageRank 
References 
0
0.34
0
Authors
10
Name
Order
Citations
PageRank
Zongwu Wang104.06
Zhezhi He213625.37
Rui Yang321.76
Shiquan Fan485.58
Jie Lin500.34
Fangxin Liu600.68
Yueyang Jia700.34
Chenxi Yuan800.34
Qidong Tang901.01
Li Jiang1028631.86