Name
Abstract | ||
|---|---|---|
Current hardware designs have increased in complexity, resulting in a reduced ability to perform security checks on them. Further, the addition of any security features to these designs is still largely manual which further complicates the design and integration process. In this paper, we address these shortcomings by introducing RTSEC as a framework which is capable of performing security analysis on designs as well as integrating security features directly into the HDL code, a feature that commercial EDA tools do not provide. RTSEC first breaks down HDL code into an Abstract Syntax Tree which is then used to infer the logic of the design. We demonstrate how RTSEC can be utilized to automatically include security mechanisms in RTL designs: watermarking and logic locking. We also compare the efficacy of our analysis algorithms with state of the art tools, demonstrating that RTSEC has capabilities equal or superior to those of state of the art tools while also providing the means of enhancing security features to the design. |
Year | DOI | Venue |
|---|---|---|
2022 | 10.23919/DATE54114.2022.9774745 | PROCEEDINGS OF THE 2022 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2022) |
DocType | ISSN | Citations |
Conference | 1530-1591 | 0 |
PageRank | References | Authors |
0.34 | 0 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Orlando Arias | 1 | 0 | 0.68 |
| Zhaoxiang Liu | 2 | 0 | 0.68 |
| Xiaolong Guo | 3 | 2 | 2.39 |
| Yier Jin | 4 | 999 | 85.70 |
| Shuo Wang | 5 | 0 | 0.34 |