Name
Abstract | ||
|---|---|---|
Analytical techniques have long been a prevailing approach to digital IC placement due to their advantage in handling large-sized problems. Recently, they have been adopted for analog IC placement, an area where prior methods were mostly based on simulated annealing. However, a comparative study between the two classes of approaches is lacking. Moreover, the effectiveness of different analytical techniques is not clear. This work attempts to shed light on both issues by studying existing methods and developing a new analytical technique. Since prior analytical methods have not addressed circuit performance, a critical concern for automated analog layout, this work also extends the new analytical placer for performance-driven placement. Experiments on various test circuits show that for a conventional performance-oblivious formulation, the proposed analytical technique achieves 55x speedup and 12% wirelength reduction compared to simulated annealing. For performance-driven placement, the proposed technique outperforms simulated annealing in terms of circuit performance, area, and runtime. Moreover, the proposed technique generally provides better solution quality than an alternative analytical technique. |
Year | DOI | Venue |
|---|---|---|
2022 | 10.23919/DATE54114.2022.9774498 | 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) |
Keywords | DocType | ISSN |
digital IC placement,analog IC placement,simulated annealing,circuit performance,automated analog layout,performance-driven placement | Conference | 1530-1591 |
ISBN | Citations | PageRank |
978-1-6654-9637-7 | 0 | 0.34 |
References | Authors | |
17 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yishuang Lin | 1 | 7 | 2.44 |
| Yaguang Li | 2 | 0 | 0.34 |
| Donghao Fang | 3 | 0 | 0.34 |
| Meghna Madhusudan | 4 | 2 | 0.75 |
| Sachin Sapatnekar | 5 | 4074 | 361.60 |
| Ramesh Harjani | 6 | 242 | 52.65 |
| Jiang Hu | 7 | 668 | 65.67 |