Name
Title | ||
|---|---|---|
Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction |
Abstract | ||
|---|---|---|
Long-latency load requests continue to limit the performance of modern high-performance processors. To increase the latency tolerance of a processor, architects have primarily relied on two key techniques: sophisticated data prefetchers and large on-chip caches. In this work, we show that: (1) even a sophisticated state-of-the-art prefetcher can only predict half of the off-chip load requests on average across a wide range of workloads, and (2) due to the increasing size and complexity of on-chip caches, a large fraction of the latency of an off-chip load request is spent accessing the on-chip cache hierarchy to solely determine that it needs to go off-chip. The goal of this work is to accelerate off-chip load requests by removing the on-chip cache access latency from their critical path. To this end, we propose a new technique called Hermes, whose key idea is to: (1) accurately predict which load requests might go off-chip, and (2) speculatively fetch the data required by the predicted off-chip loads directly from the main memory, while also concurrently accessing the cache hierarchy for such loads. To enable Hermes, we develop a new lightweight, perceptron-based off-chip load prediction technique that learns to identify off-chip load requests using multiple program features (e.g., sequence of program counters, byte offset of a load request). For every load request generated by the processor, the predictor observes a set of program features to predict whether or not the load would go off-chip. If the load is predicted to go off-chip, Hermes issues a speculative load request directly to the main memory controller once the load’s physical address is generated. If the prediction is correct, the load eventually misses the cache hierarchy and waits for the ongoing speculative load request to finish, and thus Hermes completely hides the on-chip cache hierarchy access latency from the critical path of the correctly-predicted off-chip load. Our extensive evaluation using a wide range of workloads shows that Hermes provides consistent performance improvement on top of a state-of-the-art baseline system across a wide range of configurations with varying core count, main memory bandwidth, high-performance data prefetchers, and on-chip cache hierarchy access latencies, while incurring only modest storage overhead. The source code of Hermes is freely available at: https://github.com/CMU-SAFARI/Hermes. |
Year | DOI | Venue |
|---|---|---|
2022 | 10.1109/MICRO56248.2022.00015 | 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO) |
Keywords | DocType | ISBN |
Microarchitecture,Prefetcher,Caching,Perceptron | Conference | 978-1-6654-7428-3 |
Citations | PageRank | References |
0 | 0.34 | 52 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rahul Bera | 1 | 4 | 1.04 |
| Konstantinos Kanellopoulos | 2 | 28 | 2.72 |
| Shankar Balachandran | 3 | 0 | 0.34 |
| David Novo | 4 | 0 | 0.68 |
| Ataberk Olgun | 5 | 14 | 3.47 |
| Mohammad Sadrosadati | 6 | 0 | 1.69 |
| Onur Mutlu | 7 | 9446 | 357.40 |