Paper Info
Title
LISA: Graph Neural Network based Portable Mapping on Spatial Accelerators
Abstract
Spatial accelerators, such as Coarse-Grained Reconfigurable Arrays (CGRA), provide a promising pathway to scale the performance and power efficiency of computing systems. These accelerators depend on effective compilers to take advantage of the parallelism offered by the underlying architecture. Currently, the compilers are handcrafted for spatial accelerators, which is challenging from time to market perspective, especially with the rapid increase of diverse accelerators. In this paper, we present a portable compilation framework, called LISA, that can be tuned automatically to generate quality mapping for varied spatial accelerators. Our key contribution is to automatically identify the impact of the dataflow graph (DFG) structure characteristics (representing an application) on the mapping for a new accelerator. Towards this end, we abstract the DFG structure in graph attributes, use Graph Neural Network (GNN) to analyze the graph attributes, and identify the mapping impact for an accelerator architecture with an all-encompassing global view. Finally, we augment a simulated annealing-based mapping approach to take into account the impact of DFG structure in guiding the placement of the dataflow graph nodes and the routing of the dependencies on the accelerator. Our experimental evaluation concretely demonstrates the substantial benefit of our approach compared to the state-of-the-art solutions.
Year
DOI
Venue
2022
10.1109/HPCA53966.2022.00040
2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)
Keywords
DocType
ISSN
Spatial Accelerators,CGRA,Compiler
Conference
1530-0897
ISBN
Citations 
PageRank 
978-1-6654-2028-0
0
0.34
References 
Authors
0
4
Name
Order
Citations
PageRank
Zhaoying Li121.03
Dan Wu200.34
Dhananjaya Wijerathne322.05
Tulika Mitra42714135.99