Name
Abstract | ||
|---|---|---|
Hardware faults on the regular 2-D computing array of a typical deep learning accelerator (DLA) can lead to dramatic prediction accuracy loss. Prior redundancy design approaches typically have each homogeneous redundant processing element (PE) to mitigate faulty PEs for a limited region of the 2-D computing array rather than the entire computing array to avoid the excessive hardware overhead. However, they fail to recover the computing array when the number of faulty PEs in any region exceeds the number of redundant PEs in the same region. The mismatch problem deteriorates when the fault injection rate rises and the faults are unevenly distributed. To address the problem, we propose a hybrid computing architecture (HyCA) for fault-tolerant DLAs. It has a set of dot-production processing units (DPPUs) to recompute all the operations that are mapped to the faulty PEs despite the faulty PE locations. According to our experiments, HyCA shows significantly higher reliability, scalability, and performance with less chip area penalty when compared to the conventional redundancy approaches. Moreover, by taking advantage of the flexible recomputing, HyCA can also be utilized to scan the entire 2-D computing array and detect the faulty PEs effectively at runtime. |
Year | DOI | Venue |
|---|---|---|
2022 | 10.1109/TCAD.2021.3124763 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
Deep learning accelerator (DLA),fault detection,fault tolerance,hybrid computing architecture (HyCA) | Journal | 41 |
Issue | ISSN | Citations |
10 | 0278-0070 | 0 |
PageRank | References | Authors |
0.34 | 18 | 8 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Cheng Liu | 1 | 88 | 15.87 |
| Cheng Chu | 2 | 0 | 1.01 |
| Dawen Xu | 3 | 11 | 3.45 |
| Ying Wang | 4 | 0 | 0.34 |
| Qianlong Wang | 5 | 0 | 0.34 |
| Huawei Li | 6 | 417 | 56.32 |
| Xinrong Li | 7 | 1266 | 157.76 |
| Kwang-Ting Cheng | 8 | 5755 | 513.90 |