Title
A 3nm GAAFET Analog Assisted Digital LDO with High Current Density for Dynamic Voltage Scaling Mobile Applications
Abstract
This paper presents an analog assisted digital LDO achieving high current density and fast response characteristic. A current comparator based control method enables over 10x ratio of digital current over analog current for high current density regardless of PVT condition. The proposed LDO in 3nm GAAFET CMOS technology demonstrated current density of 34.15A/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and fast transient characteristic of 38mV droop at 1A/1ns load current condition.
Year
DOI
Venue
2022
10.1109/VLSITechnologyandCir46769.2022.9830252
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
Keywords
DocType
ISSN
Digital LDO,hybrid LDO,analog assisted digital LDO,DLDO
Conference
0743-1562
ISBN
Citations 
PageRank 
978-1-6654-9773-2
0
0.34
References 
Authors
0
13
Name
Order
Citations
PageRank
Seki Kim100.34
Hyongmin Lee200.34
Yongjin Lee300.34
Dongha Lee400.34
Byeongbae Lee500.34
Jahoon Jin600.34
Susie Kim700.34
Miri Noh800.34
Kwonwoo Kang900.34
Sangho Kim1000.34
Takahiro Nomiyama1100.34
Ji-Seon Paek1200.68
Jongwoo Lee1300.68