Name
Abstract | ||
|---|---|---|
State-of-the-art EDA tools largely employ functional circuit models that are inadequate for verifying and emulating design properties related to fault effect and tolerance. In this paper, we derive fully synthesizable fault effect propagation models for formally reasoning about fault-related design behaviors under different types of faults. We associate each signal bit with a binary fault label to reflect its fault attribute. We further derive fine-granularity precise propagation policies and specify these policies as formal models for fault effect analysis using functional EDA tools. Experimental results using IWLS benchmarks have demonstrated that our formal models can be used to measure fault propagation effects and accelerate fault verification through hardware emulation. Our work makes a step towards property driven EDA flows that allow fault tolerance and dependability to be verified alongside functional correctness. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/ITC-Asia53059.2021.9808799 | 2021 IEEE International Test Conference in Asia (ITC-Asia) |
Keywords | DocType | ISSN |
Fault effect,fault propagation,formal model,property driven EDA. | Conference | 2768-0681 |
ISBN | Citations | PageRank |
978-1-6654-1335-0 | 0 | 0.34 |
References | Authors | |
8 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wei Hu | 1 | 0 | 0.68 |
| Jing Tan | 2 | 0 | 0.68 |
| Lingjuan Wu | 3 | 1 | 2.04 |
| Yu Tai | 4 | 9 | 5.92 |
| Liang Hong | 5 | 0 | 0.34 |