Paper Info
Title
SBIs: Application Access to Safe, Baremetal Interrupt Latencies<sup>*</sup>
Abstract
The continued increase in Cyber-Physical System (CPS) complexity and tightening of Size, Weight and Power (SWaP) constraints are driving the need for consolidation of software tasks onto fewer microcontrollers. Many embedded systems, prominently including those in the Internet-of-Things (IoT), use software packages from multiple untrusted sources, while their network interfaces expose new attack surfaces that are not present in traditional off-line devices. Increased consolidation with untrusted code of various assurance levels complicates system design, and requires increased spatial and temporal isolation between the applications. Current microcontroller protection domain designs are limited by their long interrupt latencies to isolated applications, forcing the system designers to place timing-sensitive application code into the kernel interrupt handlers, trading spatial isolation for tightly-bounded temporal predictability.SBI (Secure Baremetal Interrupt) enables zero-software-cost delivery of interrupts to protection domains in a secure manner that maintains isolation. We demonstrate an implementation of SBI using the new hardware-accelerated interrupt delivery features on TrustZone-M-enabled microcontrollers. This implementation reduces interrupt latencies by up to 95%, while maintaining strong spatial and temporal isolation. We believe SBI could significantly enable future real-time systems that require both isolation and high responsiveness.
Year
DOI
Venue
2022
10.1109/RTAS54340.2022.00015
2022 IEEE 28th Real-Time and Embedded Technology and Applications Symposium (RTAS)
Keywords
DocType
ISSN
interrupts,virtualization,microcontrollers,microkernel,real-time
Conference
1545-3421
ISBN
Citations 
PageRank 
978-1-6654-9999-6
0
0.34
References 
Authors
0
2
Name
Order
Citations
PageRank
Runyu Pan152.19
Gabriel Parmer201.01