Name
Title | ||
|---|---|---|
Exploiting High-Bandwidth Memory for FPGA-Acceleration of Inference on Sum-Product Networks |
Abstract | ||
|---|---|---|
Due to the memory wall becoming increasingly problematic in high-performance computing, there is a steady push to improve memory architectures, mainly focusing on better bandwidth as well as latency. One of the results of this push is the development of High-Bandwidth Memory (HBM) which is an alternative to the regular DRAM typically used by accelerator-cards. This work adapts an existing accelerator architecture for inference on Sum-Product Networks (SPN) to exploit the HBM present on more recent high-performance FPGA-accelerator cards. The evaluation shows that the use of HBM enables almost linear scaling of the performance due to the embarrassingly parallel nature of batch-wise SPN inference. It is also shown that the only hindrance to this scaling is the limited bandwidth available for data-transfers between host and FPGA. Even with this bottleneck, the prior FPGA-based implementation is outperformed by up to 1.50x (geo.-mean 1.29x). Similarly, the CPU and GPU baselines are outperformed by up to 2.4x (geo.-mean 1.6x) and 8.4x (geo.-mean 6.9x) respectively. Based on the evaluation, the scaling potential of HBM-based FPGA-accelerators is explored to give an outlook on what is to come with future generations of PCIe-based interfaces. |
Year | DOI | Venue |
|---|---|---|
2022 | 10.1109/IPDPSW55747.2022.00028 | 2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) |
Keywords | DocType | ISSN |
Sum-Product Network,Probabilistic Models,Machine Learning,High-Bandwidth Memory,FPGA | Conference | 2164-7062 |
ISBN | Citations | PageRank |
978-1-6654-9748-0 | 0 | 0.34 |
References | Authors | |
5 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Lukas Weber | 1 | 0 | 0.68 |
| Johannes Wirth | 2 | 1 | 0.73 |
| Lukas Sommer | 3 | 8 | 7.53 |
| Andreas Koch | 4 | 0 | 0.34 |