Name
Abstract | ||
|---|---|---|
The Secure Hash Algorithms (SHAs) are essential building blocks of modern cryptographic systems. The imple-mentation dimensions of secure hash algorithms are explored for different application scenarios. Cloud servers may favor an implementation with considerable throughput, while a compact implementation with acceptable speed and sustainable power is crucial for the Internet of Things (IoT). In this paper, we present an implementation of SHA-512 for FPGA platform based on Block RAM (BRAM) storage structure. Three implementation techniques are proposed to facilitate the usage of BRAMs as replacements for Look-Up Tables (LUTs) and Flip-Flops (FFs) to achieve a balanced FPGA utilization. Compared to other FPGA implementations of SHA-512, our design has one of the smallest slice consumption while maintaining a moderate but sufficient throughput for cryptographic applications like the post-processing of true random number generators (TRNGs). |
Year | DOI | Venue |
|---|---|---|
2022 | 10.1109/IPDPSW55747.2022.00031 | 2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) |
Keywords | DocType | ISSN |
SHA-512,BRAM,Folding,Reallocation | Conference | 2164-7062 |
ISBN | Citations | PageRank |
978-1-6654-9748-0 | 0 | 0.34 |
References | Authors | |
3 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mingyuan Yang | 1 | 0 | 0.34 |
| Yemeng Zhang | 2 | 0 | 0.34 |
| Bohan Yang | 3 | 7 | 3.22 |
| Hanning Wang | 4 | 1 | 0.70 |
| Shouyi Yin | 5 | 0 | 0.34 |
| Shaojun Wei | 6 | 0 | 0.34 |
| Leibo Liu | 7 | 0 | 0.34 |