Name
Abstract | ||
|---|---|---|
BSTRACTCGRAs are well-suited as hardware accelerators due to power efficiency and reconfigurability. However, their potential is limited by the inability of the compiler to map complex loop kernels onto the architectures effectively. We propose PANORAMA, a fast and scalable compiler based on a divide-and-conquer approach to generate quality mapping for complex dataflow graphs (DFG) representing loop bodies onto larger CGRAs. PANORAMA improves the throughput of the mapped loops by up to 2.6x with 8.7x faster compilation time compared to the state-of-the-art techniques. |
Year | DOI | Venue |
|---|---|---|
2022 | 10.1145/3489517.3530429 | Design Automation Conference |
DocType | Citations | PageRank |
Conference | 0 | 0.34 |
References | Authors | |
0 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dhananjaya Wijerathne | 1 | 0 | 0.34 |
| Zhaoying Li | 2 | 0 | 0.34 |
| Thilini Kaushalya Bandara | 3 | 0 | 0.34 |
| Tulika Mitra | 4 | 2714 | 135.99 |