Name
Abstract | ||
|---|---|---|
BSTRACTResistive random access memory (ReRAM) has demonstrated great promises of in-situ matrix-vector multiplications to accelerate deep neural networks. However, subject to the intrinsic properties of analog processing, most of the proposed ReRAM-based accelerators require excessive costly ADC/DAC to avoid distortion of electronic analog signals during inter-tile transmission. Moreover, due to bit-shifting before addition, prior works require longer cycles to serially calculate partial sum compared to multiplications, which dramatically restricts the throughput and is more likely to stall the pipeline between layers of deep neural networks. In this paper, we present a novel ReRAM-based photonic accelerator (PHANES) architecture, which calculates multiplications in ReRAM and parallel weighted accumulations during optical transmission. Such photonic paradigm also serves as high-fidelity analog-analog links to further reduce ADC/DAC. To circumvent the memory wall problem, we further propose a progressive bit-depth technique. Evaluations show that PHANES improves the energy efficiency by 6.09x and throughput density by 14.7x compared to state-of-the-art designs. Our photonic architecture also has great potentials for scalability towards very-large-scale accelerators. |
Year | DOI | Venue |
|---|---|---|
2022 | 10.1145/3489517.3530397 | Design Automation Conference |
DocType | Citations | PageRank |
Conference | 0 | 0.34 |
References | Authors | |
0 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yinyi Liu | 1 | 0 | 1.35 |
| Jiaqi Liu | 2 | 0 | 0.34 |
| Yuxiang Fu | 3 | 0 | 0.34 |
| Shixi Chen | 4 | 0 | 0.34 |
| Jiaxu Zhang | 5 | 0 | 0.34 |
| Jiang Xu | 6 | 704 | 61.98 |