Name
Title | ||
|---|---|---|
Exploiting Scheduling Information for Efficient High-Level Synthesis Design Space Exploration |
Abstract | ||
|---|---|---|
High-level synthesis (HLS) automatically transforms highlevel programming language into RTL design. It is widely used to program FPGAs as accelerators. HLS tools have many knobs that can be controlled by users to produce designs with different area-latency trade-offs. |
Year | DOI | Venue |
|---|---|---|
2022 | 10.1109/FCCM53951.2022.9786076 | 2022 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) |
Keywords | DocType | ISSN |
scheduling information,efficient high-level synthesis design space exploration,highlevel programming language,RTL design,HLS tools,area-latency trade-offs | Conference | 2576-2613 |
ISBN | Citations | PageRank |
978-1-6654-8333-9 | 0 | 0.34 |
References | Authors | |
1 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xingyue Qian | 1 | 0 | 0.34 |
| Jian Shi | 2 | 0 | 0.34 |
| Li Shi | 3 | 0 | 0.34 |
| Haoyang Zhang | 4 | 0 | 0.34 |
| Lijian Bian | 5 | 0 | 0.34 |
| Weikang Qian | 6 | 216 | 23.02 |