Name
Title | ||
|---|---|---|
On the benefits of Collaborative Thread Throttling and HLS-Versioning in CPU-FPGA Environments |
Abstract | ||
|---|---|---|
Cloud Environments have been constantly adopting collaborative CPU-FPGA architectures to accelerate applications by partitioning the execution of their kernels across both devices. However, exploiting the optimization techniques that both archi-tectures offer is challenging, so they must be smartly employed depending on the application at hand and the target optimization (e.g., performance or energy). Given that, this work investigates the impact of collaboratively applying thread throttling (i.e. artificially decreasing the number of active threads) on the CPU side and HLS (High-Level Synthesis)-versioning on the FPGA side. We use a multi-tenant Cloud service as our object of study, where sequence of application requests with different priorities result in DAGs of application kernels that must be executed over the heterogeneous architecture. We show that by synergistically applying thread throttling and HLS-versioning to the incoming kernels may improve the Energy-Dealy product in up to 41x over the default and non-optimized execution. |
Year | DOI | Venue |
|---|---|---|
2022 | 10.1109/SBCCI55532.2022.9893223 | 2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) |
Keywords | DocType | ISBN |
CPU-FPGA,throttling,Collaborative,TLP | Conference | 978-1-6654-8129-8 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tiago Knorst | 1 | 0 | 1.01 |
| Guilherme Korol | 2 | 3 | 5.16 |
| Michael Guilherme Jordan | 3 | 0 | 2.37 |
| Julio Costella Vicenzi | 4 | 0 | 0.68 |
| Arthur Lorenzon | 5 | 0 | 0.34 |
| Mateus Beck Rutzig | 6 | 0 | 0.68 |
| Antonio Carlos Schneider Beck | 7 | 0 | 1.01 |