Name
Abstract | ||
|---|---|---|
Network-on-Chip (NoC) is the central communication infrastructure of modern Multi-Processor Systems-on-Chip (MPSoCs), as the number of processing elements integrated on a single chip is continuously increasing. The exploration of the huge design space offered by novel NoC-based MPSoC architectures requires early and accurate system modeling and simulation. This paper introduces PANACA, an open-source highly configurable NoC simulator written in SystemC-TLM. PANACA enables fast simulation of MPSoCs using NoC-based architectures and is designed for a modular, flexible and precise modeling of network elements. It offers a wide set of accurate configurable parameters, such as topology, routing algorithm and flow control. The provided simulation and exploration management allows a detailed and automated evaluation of the huge design space. |
Year | DOI | Venue |
|---|---|---|
2022 | 10.1109/SBCCI55532.2022.9893260 | 2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI) |
Keywords | DocType | ISBN |
Simulator,Network-on-Chip,SystemC TLM,heterogeneous MPSoC | Conference | 978-1-6654-8129-8 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Julian Haase | 1 | 0 | 0.68 |
| Alexander Groß | 2 | 0 | 0.34 |
| Maximilian Feichter | 3 | 0 | 0.34 |
| Diana Göhringer | 4 | 6 | 7.88 |