Paper Info
Title
Accelerating Graphic Rendering on Programmable RISC-V GPUs
Abstract
Graphics rendering remains one of the most compute-intensive and memory-bound applications of GPUs and has been driving their push for performance and energy efficiency since its inception. Early GPU architectures focused only on accelerating graphics rendering and implemented dedicated a fixed-function rendering units. Today’s GPUs have become more programmable to address the complexity and diversity of modern graphics workloads while still accelerating several components of the graphics pipeline in fixed-function hardware.Generalizing the GPU microarchitecture and implement some of its graphics hardware blocks in software can save area that can be used to expand the generic pipeline, especially in mobile systems-on-chips environments where power and area is scarce.In this work, we propose a RISC-V-based hybrid GPU architecture that accelerates the graphics pipeline without paying the cost of a full hardware graphics pipeline. We evaluated the design on an Altera Arria 10 FPGA running at 200 MHz.
Year
DOI
Venue
2022
10.1109/HCS55958.2022.9895607
2022 IEEE Hot Chips 34 Symposium (HCS)
Keywords
DocType
ISSN
graphics rendering,compute-intensive memory-bound applications,energy efficiency,fixed-function rendering units,modern graphics workloads,fixed-function hardware,GPU microarchitecture,graphics hardware blocks,RISC-V-based hybrid GPU architecture,hardware graphics pipeline,programmable RISC-V,memory-bound applications,mobile system-on-chip environments,Altera Arria 10 FPGA,frequency 200.0 MHz
Conference
2573-203X
ISBN
Citations 
PageRank 
978-1-6654-6029-3
0
0.34
References 
Authors
0
11
Name
Order
Citations
PageRank
Blaise Tine100.34
Varun Saxena200.34
Santosh Srivatsan300.34
Joshua R. Simpson400.34
Fadi Alzammar500.34
Liam Paul Cooper600.34
Sam Jijina700.34
Swetha Rajagoplan800.34
Tejaswini Anand Kumar900.34
Jeff Young10325.82
Hyesoon Kim11149381.05