Name
Title | ||
|---|---|---|
An adaptive wide-range Time-to-Digital Converter with flexible resolution for DPLL applications |
Abstract | ||
|---|---|---|
This paper presents a wide-range time-to-digital converter (TDC) which can provide medium and small quantized steps for different wireline clock solutions. The TDC adaptively reuses the slow chain from a Vernier structure to cover $\gt4$ ns input range with only 16-pair delay cells, rendering a fast loop locking in a digital Phase-Locked Loop. Additionally, an optional 1-bit fractional TDC helps to improve the Vernier resolution by $\gt85$%, which further eases Vernier resolution requirement for more delay unit saving. Simulated in a 5nm FinFET process, the TDC consumes 0.93mW from 0.875V supply at a sampling clock of 156.25MHz. Depending on the fractional TDC on or off, the design achieves $\sim 1.8$ ps or $\sim 16$ ps resolution, respectively. |
Year | DOI | Venue |
|---|---|---|
2022 | 10.1109/MWSCAS54063.2022.9859506 | 2022 IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS) |
Keywords | DocType | ISSN |
Time-to-Digital Converter (TDC),Vernier,FinFET,digital phase-locked loop (DPLL) | Conference | 1548-3746 |
ISBN | Citations | PageRank |
978-1-6654-0280-4 | 0 | 0.34 |
References | Authors | |
3 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ping Lu | 1 | 0 | 0.34 |
| Minhan Chen | 2 | 0 | 0.34 |
| Shaishav Desai | 3 | 0 | 0.34 |