Abstract | ||
---|---|---|
Electrical Overstress (EOS) avoiding power integrated circuits (ICs) are often designed with depletion mode NMOSFET. In some applications, there can be no depletion mode NMOSFETs. From device normal operations and EOS analyses, new circuits without depletion mode devices are successfully proposed for approaching device typical operations and EOS endurances. |
Year | DOI | Venue |
---|---|---|
2022 | 10.1109/ICCE-Taiwan55306.2022.9869061 | 2022 IEEE International Conference on Consumer Electronics - Taiwan |
Keywords | DocType | ISSN |
EOS endurance power circuits,Electrical Overstress,power integrated circuits,depletion mode NMOSFET,device normal operations,EOS analyses,device typical operations | Conference | 2575-8276 |
ISBN | Citations | PageRank |
978-1-6654-7051-3 | 0 | 0.34 |
References | Authors | |
0 | 16 |
Name | Order | Citations | PageRank |
---|---|---|---|
Shao-Chang Huang | 1 | 0 | 1.69 |
Jian-Hsing Lee | 2 | 0 | 2.37 |
Ching-Ho Li | 3 | 0 | 1.01 |
Sue-Yi Chen | 4 | 0 | 1.01 |
Chih-Hsuan Lin | 5 | 0 | 1.01 |
Chun-Chih Chen | 6 | 0 | 2.03 |
Li-Fan Chen | 7 | 0 | 2.03 |
Gong-Kai Lin | 8 | 0 | 2.03 |
Chien-Wei Wang | 9 | 0 | 0.68 |
Kai-Chieh Hsu | 10 | 0 | 2.70 |
Szu-Chi Chen | 11 | 0 | 0.34 |
Shang-Chuan Pai | 12 | 0 | 0.34 |
Fu-Wei Pai | 13 | 0 | 0.34 |
Yin-Wei Peng | 14 | 0 | 1.01 |
Chih-Cherng Liao | 15 | 0 | 0.68 |
Ke-Horng Chen | 16 | 379 | 90.04 |