Name
Abstract | ||
|---|---|---|
Outsourcing Intellectual Properties (IPs) from vendors around the globe exposes System-on-Chip (SoC) designs to malicious implants like Hardware Trojans (HTs). Carefully crafted HTs with extremely rare trigger conditions evade conventional validation. While Machine Learning (ML) based validation increases detection accuracy, they themselves are vulnerable to Trojan attacks. Available detection and mitigation techniques fall short when an HT is capable of affecting multiple components of an SoC. This paper proposes an intermittent and robust HT that can attack the Network-on-Chip (NoC), the shared cache, and the cores, all at once. The proposed HT is mounted in the Network Interface (NI) of a malicious IP and can be triggered by specific inputs. Experimental evaluation shows that the proposed HT can increase packet latency by 3.44x (affecting the NoC), increase miss penalty by 15% (affecting the cache) and decrease system speedup by 10% (affecting the cores). Moreover, this paper also discusses why state-of-the-art defence mechanisms are insufficient to tackle the proposed HT and suggests better solutions. |
Year | DOI | Venue |
|---|---|---|
2022 | 10.1109/ISVLSI54635.2022.00043 | 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Keywords | DocType | ISSN |
Hardware Trojan (HT),System-on-Chip(SoC),Network-on-Chip (NoC),Last-Level Cache (LLC) | Conference | 2159-3469 |
ISBN | Citations | PageRank |
978-1-6654-6606-6 | 0 | 0.34 |
References | Authors | |
15 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Manju Rajan | 1 | 0 | 0.34 |
| Abhijit Das | 2 | 0 | 0.34 |
| John Jose | 3 | 0 | 0.34 |