Title
Adiabatic Logic-based STT-MRAM Design for IoT
Abstract
Improving the energy-efficiency of the memory can help to meet energy constraints in the Internet of Things (IoT) devices. Recently, the Spin- Transfer- Torque based Magnetoresistive Random Access Memory (STT-MRAM) has emerged as a promising solution to design low-leakage memory for IoT devices. However, the STT mechanism results in higher dynamic power consumption. This article proposes a novel sense amplifier based on adiabatic logic for the STT-MRAM design. The proposed circuit shows an average of 68.92 % energy efficiency improvement in 8x8 STT-MRAM array in the IoT frequency range 1 MHz to 50 MHz. The SPICE simulation was carried out using 45nm CMOS technology and 40nm perpendicular magnetic anisotropy (PMA) Magnetic tunnel junctions (MTJs).
Year
DOI
Venue
2022
10.1109/ISVLSI54635.2022.00053
2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Keywords
DocType
ISSN
Adiabatic logic,Sense-Amplifier,nonvolatile memory,Magnetic Tunnel Junction,STT-MRAM
Conference
2159-3469
ISBN
Citations 
PageRank 
978-1-6654-6606-6
0
0.34
References 
Authors
8
3
Name
Order
Citations
PageRank
Yang Wu18418.42
Amit Degada200.34
Himanshu Thapliyal300.34