Paper Info
Title
CorePerfDSL: A Flexible Processor Description Language for Software Performance Simulation
Abstract
Instruction set simulators (ISSs) model the functional behavior of embedded processors for early software development. While they offer high simulation speeds, an ISS usually does not model the timing behavior of the processor accurately. Existing software performance simulators are typically either specific to a certain microarchitecture or their description language mixes functional and microarchitectural aspects.In this paper, we introduce CorePerfDSL, an architecture description language (ADL) specifically designed to model the timing behavior of processor microarchitectures for software performance estimation. CorePerfDSL is clearly separated from any functional description of the modelled processor by a generic trace definition. As such, it is well suited to generate performance simulators that can be paired with an existing ISS, which supplies an execution trace. In addition, CorePerfDSL provides a high degree of flexibility, supporting the fast generation of models for various microarchitecture variants, which can be used for rapid architectural exploration. We demonstrate the flexibility of CorePerfDSL by describing several variants of a single-issue five-stage RISC-V microarchitecture and estimate their performances for a software benchmark program.
Year
DOI
Venue
2022
10.1109/FDL56239.2022.9925665
2022 Forum on Specification & Design Languages (FDL)
Keywords
DocType
ISSN
ISS,VP,ADL,Microarchitecture,Pipeline
Conference
1636-9874
ISBN
Citations 
PageRank 
978-1-6654-7333-0
0
0.34
References 
Authors
10
3
Name
Order
Citations
PageRank
Conrad Foik100.34
Daniel Mueller-Gritschneder200.68
Ulf Schlichtmann300.68