Paper Info
Title
A 56 GS/s 8-bit 0.011 mm<sup>2</sup> 4x Delta-Interleaved Switched-Capacitor DAC in 16nm FinFET CMOS
Abstract
This paper presents a compact 4x delta-interleaved switched-capacitor (SC) digital-to-analog converter (DAC) for digital-intensive transmitter architectures. To minimize area and leverage the strengths of FinFET technology, the implementation departs from the traditional current steering approach and consists mainly of inverters and sub-femtofarad switched capacitors. The DAC's architecture is based on parallel charge redistribution, and separates level generation, pulse timing and output power generation. The 16 nm FinFET 8-bit prototype occupies only 0.011 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> while running at 56 GS/s and providing up to 0.27 V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</inf> signal swing across its differential <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$100\ \Omega$</tex> load. It achieves an <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{IM3}\leq-48\, dBc$</tex> and an <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{SFDR}\geq 42\ \text{dB}$</tex> within its ≈ 10GHz output bandwidth while consuming 280mW from a single 0.85 V supply.
Year
DOI
Venue
2022
10.1109/ESSCIRC55480.2022.9911426
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)
Keywords
DocType
ISBN
Digital-to-analog converter (DAC),interleaving,switched-capacitor circuits
Conference
978-1-6654-8495-4
Citations 
PageRank 
References 
0
0.34
3
Authors
4
Name
Order
Citations
PageRank
Pietro Caragiulo121.13
Athanasios Ramkaj200.34
amin arbabian322735.52
Boris Murmann459482.64