Name
Abstract | ||
|---|---|---|
In this brief, we present a novel pipelined architecture for real-valued fast Fourier transform (RFFT), which is dedicated to processing serial input data. An optimized algorithm is proposed for stage division in RFFT to achieve an area-efficient RFFT computing structure with full hardware utilization. A single path butterfly and a real rotator are merged into one processing element (PE) in each stage, except the last stage, to reduce hardware resource utilization. In addition, a novel shift-adder is designed for
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-point RFFT with
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-bit signals, and a new data management method based on the PEs is proposed, which saves resources with a more regular flow graph. |
Year | DOI | Venue |
|---|---|---|
2022 | 10.1109/TCSII.2022.3187096 | IEEE Transactions on Circuits and Systems II: Express Briefs |
Keywords | DocType | Volume |
Fast fourier transform (FFT),real-valued signals,pipelined architecture,serial commutator | Journal | 69 |
Issue | ISSN | Citations |
11 | 1549-7747 | 0 |
PageRank | References | Authors |
0.34 | 12 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hongji Fang | 1 | 0 | 0.34 |
| Bo Zhang | 2 | 4 | 19.80 |
| Feng Yu | 3 | 16 | 6.22 |
| Bei Zhao | 4 | 0 | 0.34 |
| Zhenguo Ma | 5 | 0 | 0.34 |