Name
Title | ||
|---|---|---|
Morpheus: Extending the Last Level Cache Capacity in GPU Systems Using Idle GPU Core Resources |
Abstract | ||
|---|---|---|
Graphics Processing Units (GPUs) are widely-used accelerators for data-parallel applications. In many GPU applications, GPU memory bandwidth bottlenecks performance, causing underutilization of GPU cores. Hence, disabling many cores does not affect the performance of memory-bound workloads. While simply power-gating unused GPU cores would save energy, prior works attempt to better utilize GPU cores for other applications (ideally compute-bound), which increases the GPU’s total throughput. In this paper, we introduce Morpheus, a new hardware/software co-designed technique to boost the performance of memory-bound applications. The key idea of Morpheus is to exploit unused core resources to extend the GPU last level cache (LLC) capacity. In Morpheus, each GPU core has two execution modes: compute mode and cache mode. Cores in compute mode operate conventionally and run application threads. However, for the cores in cache mode, Morpheus invokes a software helper kernel that uses the cores’ on-chip memories (i.e., register file, shared memory, and L1) in a way that extends the LLC capacity for a running memory-bound workload. Morpheus adds a controller to the GPU hardware to forward LLC requests to either the conventional LLC (managed by hardware) or the extended LLC (managed by the helper kernel). Our experimental results show that Morpheus improves the performance and energy efficiency of a baseline GPU architecture by an average of 39% and 58%, respectively, across several memory-bound workloads. Morpheus’ performance is within 3% of a GPU design that has a quadruple-sized conventional LLC. Morpheus can thus contribute to reducing the hardware dedicated to a conventional LLC by exploiting idle cores’ on-chip memory resources as additional cache capacity. |
Year | DOI | Venue |
|---|---|---|
2022 | 10.1109/MICRO56248.2022.00029 | 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO) |
Keywords | DocType | ISBN |
GPU systems,idle GPU core resources,data-parallel applications,GPU applications,GPU memory bandwidth bottlenecks performance,memory-bound workloads,GPU's total throughput,memory-bound applications,unused core resources,GPU last level cache capacity,compute mode,cache mode,application threads,on-chip memories,shared memory,running memory-bound workload,GPU hardware,baseline GPU architecture,Morpheus' performance,GPU design,idle cores,on-chip memory resources,additional cache capacity | Conference | 978-1-6654-7428-3 |
Citations | PageRank | References |
0 | 0.34 | 58 |
Authors | ||
9 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sina Darabi | 1 | 4 | 1.42 |
| Mohammad Sadrosadati | 2 | 0 | 1.69 |
| Negar Akbarzadeh | 3 | 1 | 0.68 |
| Joël Lindegger | 4 | 1 | 0.68 |
| Mohammad Hosseini | 5 | 0 | 0.34 |
| Jisung Park | 6 | 40 | 6.96 |
| Juan Gómez-Luna | 7 | 22 | 3.88 |
| Onur Mutlu | 8 | 9446 | 357.40 |
| Hamid Sarbazi-Azad | 9 | 949 | 103.28 |