Name
Abstract | ||
|---|---|---|
Today, FPGA vendors provide a C++/C-based programming environment to enhance programmer productivity over using a hardware-description language at the register-transfer level. The common perception is that this enhanced pro-ductivity comes at the expense of significantly less performance, e.g., as much an order of magnitude worse. To characterize this performance-productivity tradeoff, we propose a new composite metric, II, that quantitatively captures the perceived discrepancy between the performance and productivity of any two given FPGA programming languages, e.g., Verilog vs. OpenCL. We then present the implications of our metric via a case study on the design of a Sobel filter (i.e., edge detector) using three different programming models - Verilog, OpenCL, oneAPI - on an Intel Arria 10 GX FPGA accelerator. Relative to performance, our results show that an optimized OpenCL kernel achieves 84% of the performance of an optimized Verilog version of the code on a 7680×4320 (8K) image. Conversely, relative to productivity, OpenCL offers a 6.1 x improvement in productivity over Verilog, while oneAPI improves the productivity by an additional factor of 1.25 x over OpenCL. |
Year | DOI | Venue |
|---|---|---|
2022 | 10.1109/HPEC55821.2022.9926404 | 2022 IEEE High Performance Extreme Computing Conference (HPEC) |
Keywords | DocType | ISSN |
FPGA,hardware-description language (HDL),high-level synthesis (HLS),oneAPI,OpenCL,Verilog,performance,productivity,register-transfer level (RTL),SLOC | Conference | 2377-6943 |
ISBN | Citations | PageRank |
978-1-6654-9787-9 | 0 | 0.34 |
References | Authors | |
12 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Atharva Gondhalekar | 1 | 0 | 0.34 |
| Thomas Twomey | 2 | 0 | 0.34 |
| Wu-chun Feng | 3 | 2812 | 232.50 |