Author Info
Name
Affiliation
Papers
CHAITALI CHAKRABARTI
Arizona State Univ, Dept Elect Engn, Tempe, AZ 85287 USA
1
Collaborators
Citations 
PageRank 
1
11
0.86
Referers 
Referees 
References 
31
14
4
Title
Citations
PageRank
Year
A leakage estimation and reduction technique for scaled CMOS logic circuits considering gate-leakage110.862004