Name
Title | ||
|---|---|---|
A leakage estimation and reduction technique for scaled CMOS logic circuits considering gate-leakage |
Abstract | ||
|---|---|---|
Leakage power reduction is extremely important in the design of scaled CMOS logic circuits. The dominant leakage mechanism of such circuits is the gate leakage. This paper first describes a fast leakage estimation technique based on biasing states for both gate leakage and sub-threshold leakage. Next, it describes a leakage reduction method based on the selective insertion of control points. Simulations on a set of examples show that this method results in the average leakage being 28.7% of the leakage of the baseline circuit whose inputs have already been subjected to the minimum leakage vector (MLV). |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/ISCAS.2004.1329267 | Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium |
Keywords | Field | DocType |
CMOS logic circuits,circuit simulation,leakage currents,parameter estimation,baseline circuit leakage,control point selective insertion,gate leakage,leakage estimation,leakage mechanism,leakage power reduction,minimum leakage vector,scaled CMOS logic circuit design,subthreshold leakage | Logic gate,Leakage (electronics),Computer science,Electronic engineering,Subthreshold conduction,Estimation theory,Electronic circuit,Threshold voltage,Electrical engineering,Low-power electronics,Biasing | Conference |
Volume | ISBN | Citations |
2 | 0-7803-8251-X | 11 |
PageRank | References | Authors |
0.86 | 4 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hafijur Rahman | 1 | 11 | 0.86 |
| Chaitali Chakrabarti | 2 | 11 | 0.86 |