Author Info
Name
Affiliation
Papers
KYOMIN SOHN
Memory Division, DRAM Design Team, Samsung Electronics, Hwaseong, South Korea
2
Collaborators
Citations 
PageRank 
30
1
0.71
Referers 
Referees 
References 
5
116
16
Search Limit
100116
Title
Citations
PageRank
Year
A 5 Gb/s Time-Interleaved Voltage-Mode Duobinary Encoding Scheme for 3-D-Stacked IC00.342022
A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme10.372021