Author Info
Name
Papers
Collaborators
YIQUN ZHU
2
5
Citations 
PageRank 
Referers 
6
0.93
17
Referees 
References 
54
25
Title
Citations
PageRank
Year
Hardware Implementations with High Throughput, Low-Latency and Low-Area for Matrix Inversion.00.342020
Reconfigurable Hardware Architectures for Sequential and Hybrid Decoding60.592007