Name
Abstract | ||
|---|---|---|
A novel reconfigurable sequential decoder architecture based on the Fano algorithm is presented in which the constraint length, the threshold spacing, and the time-out threshold are all run time reconfigurable. To maximize decoding performance, a maximum possible backward depth (of a whole frame) is performed. This is achieved by using shift registers combined with memory to store the information of an entire visited path. A field-programmable gate array) prototype of the decoder is built and actual hardware decoding performances in terms of decoding speeds, bit error rates (BERs), and buffer overflow rates, are obtained and comparisons made. To overcome the decoding delay that is inherent in sequential decoders, a hybrid scheme, including simple block codes and cyclic redundancy check is proposed to limit the number of backward search operations that the sequential decoder has to execute. As a result, a significant reduction in decoding delay and buffer overflow rate is achieved while maintaining comparative decoding performance in terms of BER |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/TCSI.2006.887600 | Circuits and Systems I: Regular Papers, IEEE Transactions |
Keywords | Field | DocType |
block codes,buffer circuits,cyclic redundancy check codes,error statistics,field programmable gate arrays,reconfigurable architectures,sequential decoding,shift registers,BER,Fano algorithm,bit error rates,block codes,buffer overflow rate,constraint length,cyclic redundancy check codes,decoding delay,field-programmable gate array,hybrid decoding,reconfigurable hardware architectures,reconfigurable sequential decoder architecture,sequential decoding,shift registers,threshold spacing,time-out threshold,Error correcting codes,Fano decoding,field-programmable gate array (FPGA),hybrid decoding,reconfigurable design,sequential decoding | Sequential decoding,Cyclic redundancy check,Computer science,Block code,Electronic engineering,Soft-decision decoder,Decoding methods,List decoding,Reconfigurable computing,Buffer overflow | Journal |
Volume | Issue | ISSN |
54 | 3 | 1549-8328 |
Citations | PageRank | References |
6 | 0.59 | 25 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| M. Benaissa | 1 | 27 | 2.62 |
| Yiqun Zhu | 2 | 6 | 0.93 |