Jong-Kwan Woo - Citegraph

Author Info

Name	Affiliation	Papers
JONG-KWAN WOO	Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI, USA	12
Collaborators	Citations	PageRank
25	23	5.63
Referers	Referees	References
82	204	74

Search Limit

100204

Publications (12 rows)

Collaborators (25 rows)

Referers (82 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A 9-bit, 110-MS/s pipelined-SAR ADC using time-interleaved technique with shared comparator	0	0.34	2015
1.2 V 10-bit 75 MS/s Pipelined ADC With Phase-Dependent Gain-Transition CDS	0	0.34	2014
A 10-Mbps 0.8-pJ/bit Referenceless Clock and Data Recovery Circuit for Optically Controlled Neural Interface System	0	0.34	2013
High-resolution and wide-dynamic range time-to-digital converter with a multi-phase cyclic Vernier delay line	1	0.35	2013
Power-Gating Noise Minimization by Three-Step Wake-Up Partitioning.	3	0.45	2012
A Low-Cost and Low-Power Time-to-Digital Converter Using Triple-Slope Time Stretching	9	0.72	2011
A comparator-based cyclic analog-to-digital converter with boosted preset voltage	4	0.61	2011
A low-power referenceless clock and data recovery circuit with clock-edge modulation for biomedical sensor applications	1	0.41	2011
A CMOS readout integrated circuit with wide dynamic range for a CNT bio-sensor array system	0	0.34	2011
Charge Amplifier With an Enhanced Frequency Response for SPM-Based Data Storage	1	0.63	2010
A high-resolution and fast-conversion readout circuit for differential capacitive sensors	0	0.34	2010
A 14.6 ps Resolution, 50 ns Input-Range Cyclic Time-to-Digital Converter Using Fractional Difference Conversion Method.	4	0.77	2010

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