Title
Power-Gating Noise Minimization by Three-Step Wake-Up Partitioning.
Abstract
Power gating is able to counter subthreshold leakage in low-power nanometer technology circuits without sacrificing performance. But mode transitions in power-gated circuits are accompanied by large inrush/discharge currents causing inductive bounce noise on the power supply and ground rails. This issue has been addressed by gradually turning on the sleep transistor; but this introduces a fixed lo...
Year
DOI
Venue
2012
10.1109/TCSI.2011.2169889
IEEE Transactions on Circuits and Systems I: Regular Papers
Keywords
Field
DocType
Noise,Rails,Switching circuits,Transistors,Power supplies,Capacitance,Logic gates
Ground bounce,Logic gate,Inrush current,Electronic engineering,CMOS,Power gating,Subthreshold conduction,Transistor,Electronic circuit,Electrical engineering,Mathematics
Journal
Volume
Issue
ISSN
59
4
1549-8328
Citations 
PageRank 
References 
3
0.45
20
Authors
5
Name
Order
Citations
PageRank
Rahul Singh1111.47
Jong-Kwan Woo2235.63
Hyunjoong Lee37315.92
Soyoung Kim416822.15
Suhwan Kim549474.23