J. A. Fifield - Citegraph

Author Info

Publications (3 rows)

Collaborators (24 rows)

Referers (99 rows)

Referees (90 rows)

Title	Citations	PageRank	Year
A 45nm Soi Compiled Embedded Dram With Random Cycle Times Down To 1.3ns	2	0.44	2010
A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST	1	0.40	2007
A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining	15	3.51	2005