Name
Abstract | ||
|---|---|---|
A family of embedded DRAMs which are fabricated in 45nm SOI technology is presented. The fast eDRAM has 64 b/BL and achieves a random cycle time of 1.3ns for V-DD = 1.00V and typical process. The dense eDRAM has 128 b/BL and operates in multi-bank modes up to 1.67GHz for V-DD = 1.0V and nominal process. The staggered - folded BL architecture with BL twisting over both the array and SAs is described as well as a novel wordline timer which generates a 75% duty cycle signal from a 50% duty cycle clock. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/CICC.2010.5617634 | IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE 2010 |
Keywords | Field | DocType |
silicon on insulator,cycle time,duty cycle,capacitance,embedded systems,capacitors,random processes | Dram,Silicon on insulator,Capacitor,Capacitance,Computer science,Duty cycle,Stochastic process,Electronic engineering,eDRAM,Timer | Conference |
Citations | PageRank | References |
2 | 0.44 | 6 |
Authors | ||
11 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mark Jacunski | 1 | 2 | 0.78 |
| Darren Anand | 2 | 15 | 3.01 |
| Robert Busch | 3 | 2 | 0.44 |
| J. A. Fifield | 4 | 18 | 4.35 |
| Matthew Lanahan | 5 | 2 | 0.44 |
| Paul Lane | 6 | 2 | 0.44 |
| Adrian Paparelli | 7 | 5 | 0.91 |
| Gary Pomichter | 8 | 12 | 1.90 |
| Dale Pontius | 9 | 2 | 0.78 |
| Michael Roberge | 10 | 5 | 1.59 |
| Stephen Sliva | 11 | 5 | 0.91 |