Rafail Lashevsky - Citegraph

Author Info

Name	Affiliation	Papers
RAFAIL LASHEVSKY	Logic Design Laboratory, The University of Aizu 965-8580 Japan JP	2
Collaborators	Citations	PageRank
3	0	0.68
Referers	Referees	References
0	0	0

Publications (2 rows)

Collaborators (3 rows)

Referers (0 rows)

Referees (0 rows)

Title	Citations	PageRank	Year
Deviation-tolerant floating gate structures as a way to design an on-chip learning neural networks	0	0.34	2002
The efficiency of neuron-MOS transistors in threshold logic	0	0.34	1999

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