| INTIACC: A 32-bit Floating-Point Programmable Custom-ISA Accelerator for Solving Classes of Partial Differential Equations | 0 | 0.34 | 2022 |
| DIMC: 2219TOPS/W 2569F2/b Digital In-Memory Computing Macro in 28nm Based on Approximate Arithmetic Hardware. | 0 | 0.34 | 2022 |
| Improving DNN Hardware Accuracy by In-Memory Computing Noise Injection | 0 | 0.34 | 2022 |
| Review, Survey, and Benchmark of Recent Digital LDO Voltage Regulators | 0 | 0.34 | 2022 |
| MPAM: Reliable, Low-Latency, Near-Threshold-Voltage Multi-Voltage/Frequency-Domain Network-on-Chip with Metastability Risk Prediction and Mitigation | 0 | 0.34 | 2022 |
| A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks | 0 | 0.34 | 2022 |
| Channel Estimation Using Deep Learning on an FPGA for 5G Millimeter-Wave Communication Systems | 0 | 0.34 | 2022 |
| <sc>FLEET</sc>—Fast Lanes for Expedited Execution at 10 Terabits: Program Overview | 0 | 0.34 | 2021 |
| 0.5–1-V, 90–400-mA, Modular, Distributed, 3 × 3 Digital LDOs Based on Event-Driven Control and Domino Sampling and Regulation | 1 | 0.35 | 2021 |
| Session 29 Overview - Digital Circuits for Computing, Clocking and Power Management DIGITAL CIRCUITS SUBCOMMITTEE. | 0 | 0.34 | 2021 |
| C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism | 16 | 0.78 | 2020 |
| Memnas: Memory-Efficient Neural Architecture Search With Grow-Trim Learning | 0 | 0.34 | 2020 |
| A Bi-Directional, Zero-Latency Adaptive Clocking Circuit in a 28-nm Wide AVFS System | 0 | 0.34 | 2020 |
| Vesti: Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks | 6 | 0.44 | 2020 |
| Catena: A Near-Threshold, Sub-0.4-mW, 16-Core Programmable Spatial Array Accelerator for the Ultralow-Power Mobile and Embedded Internet of Things | 1 | 0.35 | 2020 |
| Always-On, Sub-300-nW, Event-Driven Spiking Neural Network based on Spike-Driven Clock-Generation and Clock- and Power-Gating for an Ultra-Low-Power Intelligent Device | 2 | 0.36 | 2020 |
| XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks | 25 | 0.91 | 2020 |
| Introduction to the Special Issue on the 2019 IEEE International Solid-State Circuits Conference (ISSCC) | 0 | 0.34 | 2020 |
| A Femto/Pico-Watt Feedforward Leakage Self-Suppression Logic Family in 180 nm to 28 nm Technologies | 0 | 0.34 | 2019 |
| Catena: A 0.5-V Sub-0.4-mW 16-Core Spatial Array Accelerator for Mobile and Embedded Computing | 0 | 0.34 | 2019 |
| XNOR-SRAM: In-Bitcell Computing SRAM Macro based on Resistive Computing Mechanism | 1 | 0.35 | 2019 |
| A 923 Gbps/W, 113-Cycle, 2-Sbox Energy-efficient AES Accelerator in 28nm CMOS | 0 | 0.34 | 2019 |
| Cases for Analog Mixed Signal Computing Integrated Circuits for Deep Neural Networks | 0 | 0.34 | 2019 |
| Design of an Always-On Deep Neural Network-Based 1-<inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math></inline-formula>W Voice Activity Detector Aided With a Customized Software Model for Analog Feature Extraction | 7 | 0.47 | 2019 |
| A 0.5-1V Input Event-Driven Multiple Digital Low-Dropout-Regulator System for Supporting a Large Digital Load | 1 | 0.35 | 2019 |
| A Near-Threshold Spiking Neural Network Accelerator With a Body-Swapping-Based <inline-formula> <tex-math notation="LaTeX">$In \,\,Situ$ </tex-math></inline-formula> Error Detection and Correction Technique | 0 | 0.34 | 2019 |
| Recursive Binary Neural Network Training Model for Efficient Usage of On-Chip Memory | 0 | 0.34 | 2019 |
| Ultra-Low-Power Intelligent Acoustic Sensing using Cochlea-Inspired Feature Extraction and DNN Classification | 1 | 0.36 | 2019 |
| Vesti: An In-Memory Computing Processor For Deep Neural Networks Acceleration | 0 | 0.34 | 2019 |
| An Area-Efficient Microprocessor-Based SoC With an Instruction-Cache Transformable to an Ambient Temperature Sensor and a Physically Unclonable Function. | 4 | 0.40 | 2018 |
| Blacklist Core: Machine-Learning Based Dynamic Operating-Performance-Point Blacklisting for Mitigating Power-Management Security Attacks | 2 | 0.40 | 2018 |
| 0.5V-VIN, 165-MA/MM2 Fully-Integrated Digital LDO Based on Event-Driven Self-Trisuerina Control. | 0 | 0.34 | 2018 |
| KTAN: Knowledge Transfer Adversarial Network. | 2 | 0.36 | 2018 |
| Corrections to "Energy-Efficient Hybrid Analog/Digital Approximate Computation in Continuous Time". | 0 | 0.34 | 2018 |
| In~Situ and In-Field Technique for Monitoring and Decelerating NBTI in 6T-SRAM Register Files. | 0 | 0.34 | 2018 |
| A 0.78-µW 96-Ch. Deep Sub-Vt Neural Spike Processor Integrated with a Nanowatt Power Management Unit. | 0 | 0.34 | 2018 |
| Recent advances in in-situ and in-field aging monitoring and compensation for integrated circuits: Invited paper | 0 | 0.34 | 2018 |
| High-Capacity Fingerprint Recognition System based on a Dynamic Memory-Capacity Estimation Technique. | 0 | 0.34 | 2018 |
| A Case Study in Analog Co-Processing for Solving Stochastic Differential Equations. | 1 | 0.39 | 2018 |
| 20.6 A 0.5V-VIN 1.44mA-class event-driven digital LDO with a fully integrated 100pF output capacitor. | 0 | 0.34 | 2017 |
| Compact and voltage-scalable sensor for accurate thermal sensing in dynamic thermal management | 0 | 0.34 | 2017 |
| A 0.17-mm2 3.19-nJ/transform 256-point fast fourier transform core based on spatiotemporally fine-grained active leakage suppression. | 0 | 0.34 | 2017 |
| A Fully Integrated Digital Low-Dropout Regulator Based on Event-Driven Explicit Time-Coding Architecture. | 4 | 0.44 | 2017 |
| Dynamic Capacity Estimation in Hopfield Networks. | 0 | 0.34 | 2017 |
| Pipelining a triggered processing element. | 3 | 0.36 | 2017 |
| A Technique To Transform 6t-Sram Arrays Into Robust Analog Puf With Minimal Overhead | 0 | 0.34 | 2017 |
| An area-efficient microcontroller with an instruction-cache transformable to an ambient temperature sensor and a physically unclonable function | 0 | 0.34 | 2017 |
| Triple-Mode, Hybrid-Storage, Energy Harvesting Power Management Unit: Achieving High Efficiency Against Harvesting and Load Power Variabilities. | 1 | 0.35 | 2017 |
| Recursive Binary Neural Network Learning Model with 2.28b/Weight Storage Requirement. | 0 | 0.34 | 2017 |
| Extending memory capacity of neural associative memory based on recursive synaptic bit reuse. | 0 | 0.34 | 2017 |
