Exploiting Parametric Power Supply and/or Temperature Variations to Improve Fault Tolerance in Digital Circuits | 2 | 0.39 | 2008 |
Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-level | 7 | 0.58 | 2001 |
Optimizing Functional distribution in Complex System Design | 1 | 0.37 | 2000 |
Realistic Fault Extraction for High-Quality Design and Test of VLSI Systems | 15 | 1.40 | 1997 |
Back Annotation of Physical Defects into Gate-Level, Realistic Faults in Digital ICs | 7 | 0.65 | 1994 |
Realistic Fault Analysis of CMOS Analog Building Blocks | 1 | 0.41 | 1993 |
Experiments on Bridging Fault Analysis and Layout-Level DFT for CMOS Designs | 8 | 0.71 | 1993 |
Physical DFT for High Coverage of Realistic Faults | 18 | 1.52 | 1992 |