| Quantitative characterization of the software layer of a HW/SW co-designed processor | 0 | 0.34 | 2016 |
| Speculative hardware/software co-designed floating-point multiply-add fusion | 4 | 0.39 | 2014 |
| Accurate off-line phase classification for HW/SW co-designed processors | 0 | 0.34 | 2014 |
| Warm-Up Simulation Methodology for HW/SW Co-Designed Processors | 3 | 0.38 | 2014 |
| Performance analysis and predictability of the software layer in dynamic binary translators/optimizers | 4 | 0.38 | 2013 |
| Programming Abstractions and Toolchain for Dataflow Multithreading Architectures | 4 | 0.40 | 2009 |
| HelperCoreDB: Exploiting multicore technology to improve database performance | 0 | 0.34 | 2008 |
| TFlux: A Portable Platform for Data-Driven Multithreading on Commodity Multicore Systems | 19 | 0.97 | 2008 |
| HelperCore_DB: Exploiting Multicore Technology for Databases | 4 | 0.47 | 2007 |
| Thermal-aware scheduling for future chip multiprocessors | 23 | 1.01 | 2007 |
| Chip multiprocessor based on data-driven multithreading model | 8 | 0.64 | 2007 |
| Hardware budget and runtime system for data-driven multithreaded chip multiprocessor | 1 | 0.42 | 2006 |
| Thermal-Aware Scheduling: A Solution for Future Chip Multiprocessors Thermal Problems | 16 | 0.88 | 2006 |
| A case for chip multiprocessors based on the data-driven multithreading model | 6 | 0.65 | 2006 |
| DDM-CMP: data-driven multithreading on a chip multiprocessor | 6 | 0.48 | 2005 |
| TSIC: thermal scheduling simulator for chip multiprocessors | 5 | 0.52 | 2005 |
