| IBM POWER9 circuit design and energy optimization for 14-nm technology. | 2 | 0.40 | 2018 |
| The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4. | 1 | 0.35 | 2018 |
| 3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4 | 2 | 0.55 | 2017 |
| A system of array families and synthesized soft arrays for the POWER9™ processor in 14nm SOI FinFET technology. | 0 | 0.34 | 2017 |
| 26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection. | 0 | 0.34 | 2017 |
| Sharing And Re-Use Of Statistical Timing Macro-Models Across Multiple Voltage Domains | 0 | 0.34 | 2016 |
| Session 8 overview: Low-power digital circuits | 0 | 0.34 | 2016 |
| F6: I/O design at 25Gb/s and beyond: Enabling the future communication infrastructure for big data | 1 | 0.43 | 2015 |
| IBM POWER8 circuit design and energy optimization | 1 | 0.37 | 2015 |
| Physical design and implementation of POWER8™ (P8) server class processor | 1 | 0.38 | 2015 |
| 5.1 POWER8 TM : A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth | 11 | 1.09 | 2014 |
| F3: Adaptive design techniques for energy efficiency | 0 | 0.34 | 2014 |
| Session 3 overview: Processors | 0 | 0.34 | 2013 |
| Power-constrained high-frequency circuits for the IBM POWER6 microprocessor | 3 | 0.79 | 2007 |
| Design of the Power6 Microprocessor. | 56 | 8.70 | 2007 |
