A low-area switched-resistor loop-filter technique for fractional-N synthesizers applied to a MEMS-based programmable oscillator | 5 | 0.77 | 2010 |
A Low Area, Switched-Resistor Based Fractional-N Synthesizer Applied to a MEMS-Based Programmable Oscillator | 4 | 0.80 | 2010 |
A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR | 17 | 3.78 | 2007 |
A new technique for characterization of digital-to-analog converters in high-speed systems | 3 | 0.58 | 2007 |
A 2.5Gb/s Multi-Rate 0.25/spl mu/m CMOS CDR Utilizing a Hybrid Analog/Digital Loop Filter | 1 | 0.51 | 2006 |
A 2.5-Gb/s Multi-Rate 0.25-<formula><tex>$\mu$</tex></formula>m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition | 14 | 1.43 | 2006 |
Modeling, Simulation, and Design of a Multi-Mode 2-10 Gb/sec Fully Adaptive Serial Link System | 3 | 0.76 | 2005 |