Name
Title | ||
|---|---|---|
A 2.5-Gb/s Multi-Rate 0.25-<formula><tex>$\mu$</tex></formula>m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition |
Abstract | ||
|---|---|---|
A 0.25-mum CMOS, multi-rate clock and data recovery (CDR) circuit that leverages unique analog/digital boundaries in its phase detector and loop filter to achieve a fully integrated CDR implementation with excellent performance, compact area, and low power dissipation is presented. Key circuit blocks include a phase-to-digital converter that combines a Hogge detector with a continuous-time first-o... |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/JSSC.2006.884391 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
Phase detection,Detectors,Digital filters,Analog-digital conversion,Frequency estimation,Bit error rate,CMOS digital integrated circuits,CMOS analog integrated circuits,Clocks,Power dissipation | Journal | 41 |
Issue | ISSN | Citations |
12 | 0018-9200 | 14 |
PageRank | References | Authors |
1.43 | 7 | 12 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Michael H. Perrott | 1 | 110 | 19.50 |
| Yunteng Huang | 2 | 14 | 1.43 |
| Rex T. Baird | 3 | 35 | 10.41 |
| Bruno W. Garlepp | 4 | 47 | 8.61 |
| Douglas F. Pastorello | 5 | 14 | 1.76 |
| Eric T. King | 6 | 14 | 1.43 |
| Qicheng Yu | 7 | 31 | 5.54 |
| Dan B. Kasha | 8 | 14 | 1.43 |
| Philip Steiner | 9 | 21 | 2.53 |
| Ligang Zhang | 10 | 169 | 19.58 |
| Jerrell Hein | 11 | 14 | 1.43 |
| Bruce Del Signore | 12 | 14 | 1.43 |