Ren-Shuo Liu - Citegraph

Author Info

Name	Affiliation	Papers
REN-SHUO LIU	National Taiwan University, Taipei, Taiwan	19
Collaborators	Citations	PageRank
119	141	9.86
Referers	Referees	References
396	410	162

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100410

Publications (19 rows)

Collaborators (100 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI Devices	1	0.41	2022
A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices	1	0.38	2022
A 28nm 384kb 6t-Sram Computation-In-Memory Macro With 8b Precision For Ai Edge Chips	1	0.35	2021
Value-Aware Error Detection and Correction for SRAM Buffers in Low-Bitwidth, Floating-Point CNN Accelerators	0	0.34	2021
A 22nm 4mb 8b-Precision Reram Computing-In-Memory Macro With 11.91 To 195.7tops/W For Tiny Ai Edge Devices	1	0.34	2021
15.5 A 28nm 64kb 6t Sram Computing-In-Memory Macro With 8b Mac Operation For Ai Edge Chips	1	0.35	2020
15.4 A 22nm 2mb Reram Compute-In-Memory Macro With 121-28tops/W For Multibit Mac Computing For Tiny Ai Edge Devices	0	0.34	2020
5.9 A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel	0	0.34	2020
15.2 A 28nm 64kb Inference-Training Two-Way Transpose Multibit 6t Sram Compute-In-Memory Macro For Ai Edge Chips	0	0.34	2020
A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors.	0	0.34	2019
Long-Term JPEG Data Protection and Recovery for NAND Flash-Based Solid-State Storage	0	0.34	2019
DI-SSD: Desymmetrized interconnection architecture and dynamic timing calibration for solid-state drives	0	0.34	2018
VST: A virtual stress testing framework for discovering bugs in SSD flash-translation layers.	0	0.34	2017
Improving Read Performance of NAND Flash SSDs by Exploiting Error Locality.	8	0.48	2016
NVM duet: unified working memory and persistent store architecture	36	1.12	2014
EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs	10	0.49	2014
DuraCache: A durable SSD cache using MLC NAND flash	20	0.80	2013
Optimizing NAND flash-based SSDs via retention relaxation	62	2.09	2012
Parallelization and characterization of GARCH option pricing on GPUs	0	0.34	2010

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