| Designing Efficient Parallel Processing in 3D Standard-Chip Stacking System with Standard Bus | 0 | 0.34 | 2017 |
| Impact of die thinning on the thermal performance of a central TSV bus in a 3D stacked circuit | 1 | 0.38 | 2015 |
| Investigation of optimized high-density flip-chip interconnect design including micro Au bumps for 3-D stacked LSI packaging | 0 | 0.34 | 2013 |
| New optical three dimensional structure measurement method of cone shape micro bumps used for 3D LSI chip stacking | 0 | 0.34 | 2013 |
| PDN impedance analysis of TSV-decoupling capacitor embedded Silicon interposer for 3D-integrated CMOS image sensor system. | 0 | 0.34 | 2011 |
| COOL interconnect low power interconnection technology for scalable 3D LSI design | 3 | 0.74 | 2011 |
| Hot spots suppression by high thermal conductivity film in thin-sub strate CMOS ICs for 3D integration | 0 | 0.34 | 2011 |
| Ultralow Impedance Evaluation System Of Wideband Frequency For Power Distribution Network Of Decoupling Capacitor Embedded Substrates | 0 | 0.34 | 2009 |
| SrTiO3 thin film decoupling capacitors on Si interposers for 3D system integration. | 0 | 0.34 | 2009 |
| Chemical Flip-Chip Bonding Method For Fabricating 10-Mu M-Pad-Pitch Interconnect | 0 | 0.34 | 2008 |
| Band-Stop Filter Effect Of Power/Ground Plane On Through-Hole Signal Via In Multilayer Pcb | 0 | 0.34 | 2006 |
