A. Biasizzo - Citegraph

Author Info

Name	Affiliation	Papers
A. BIASIZZO	Jožef Stefan Institute, Jamova 39, 1000 Ljubljana, Slovenia	17
Collaborators	Citations	PageRank
21	52	8.08
Referers	Referees	References
146	264	110

Search Limit

100264

Publications (17 rows)

Collaborators (21 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Hardware accelerated compression of LIDAR data using FPGA devices.	0	0.34	2013
Test Strategies for Embedded ADC Cores in a System-on-Chip, A Case Study.	0	0.34	2012
On-Line Self-Recovery Of Embedded Multi-Processor Soc On Fpga Using Dynamic Partial Reconfiguration	1	0.36	2012
A compact AES core with on-line error-detection for FPGA applications with modest hardware resources	7	0.53	2011
FPGA Soft Error Recovery Mechanism with Small Hardware Overhead	1	0.36	2011
Soft Error Recovery Technique for Multiprocessor SOPC	0	0.34	2011
Self-reparable system on FPGA for single event upset recovery.	2	0.39	2011
On measurement uncertainty of ADC nonlinearities in oscillation-based test	1	0.36	2010
Functional Testing of Processor Cores in FPGA-Based Applications	3	0.56	2009
Security Extension for IEEE Std 1149.1	16	1.08	2006
Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in Europe	0	0.34	2004
Linux-based experimental boundary scan environment	1	0.43	2002
A methodology for model-based diagnosis of analog circuits	2	0.41	2000
On The Diagnosing Algorithm For Networks	0	0.34	2000
Sequential diagnosis tool	8	0.78	2000
Sequential Diagnosis with Asymmetrical Tests	5	0.57	1998
Enhancing design-for-test for active analog filters by using CLP	5	0.56	1993

1